The present invention relates generally to test data compression in manufacture testing, and, more particularly, to a test data compression method for System-on-Chip (SoC) using linear-feedback shift register reseeding.
The following works by others are mentioned in the application and referred to by their associated reference:    [1] J. Rajski, I. Tyszer, M. Kassab, and N. Mukherjee, “Embedded deterministic test,” in IEEE Tran. CAD, vol. 23, pp. 776-792, May 2004.    [2] E. J. Marinissen, R. Kapur, M. Lousberg, T. McLaurin, M. Ricchetti, and Y. Zorian, “On IEEE 1500's standard for embedded core test,” in Journal of Electronic Testing: Theory and Applications (JETTA), vol. 18, pp. 365-383, August 2002.    [3] V. Iyengar, K. Chakrabarty, and E. J. Marinissen, “Test access mechanism optimization, test scheduling, and tester data volume reduction for System-on-Chip,” in IEEE Trans. Computers, vol. 52, pp. 1619-1632, December 2003.    [4] A. B. Kinsman and N. Nicolici, “Time-multiplexed test data decompression architecture for core-based socs with improved utilization of tester channels,” in Proc. European Test Symp., 2005, pp. 196-201.    [5] P. T. Gonciari and B. M. Al-Hashimi, “A compression-driven test access mechanism design approach,” in Proc. European Test Symp., 2004, pp. 100-105.    [6] E. H. Volkerink and S. Mitra, “Efficient seed utilization for reseeding based compression,” in Proc. VTS 2003, pp. 232-237.
Test data compression has been widely used in manufacturing testing. To achieve high reduction in both test data volume and test application time, some state-of-the-art compression techniques such as [1] usually use special test generation tools to generate test patterns that are suitable to achieve maximum compression. The configuration of scan chains is also optimized for better compression results. However, when testing System-on-Chip (SoC) devices, these flexibilities are usually not available because no structural information is available for some intellectual property (IP) cores, especially, hard cores that are delivered in the form of layouts and whose scan chain configurations cannot be modified.
In addition to the problem of limited applicability of existing test compression techniques, restricted access to internal cores is another issue in SoC testing. To tackle with this restriction, test access mechanism (TAM) and test wrappers have been proposed as key components of an SoC test architecture [2]. Many techniques have been proposed to co-optimize TAM/wrapper design and test scheduling to reduce test application time for SoCs [3]. However, these techniques either do not consider test data compression, or utilize less efficient compression techniques.
Intuitively, the SoC integrator has the flexibility to combine test data compression, TAM/wrapper design, and test scheduling into a unified problem formulation, and hence to achieve decreased test data volume and test application time for the entire SoC. Prior work [4] presents a time-multiplexing technique to reduce test application for SoCs that support test data compression. The major drawback of [4] is that extra data and on-Chip hardware are needed to enable the time-multiplexing mechanism. To keep the multiplexing mechanism easy-to-implement, [4] resorts to fixed length blocks, which will however decrease the encoding efficiency. An optimal block length for one core is not necessarily optimal for other cores. Prior work [5] uses XOR network called XNet for compression, which is less efficient for high compression. It also requires two different data streams from the ATE: data and load control streams.
The diagram 10 of FIG. 1 shows the core configuration for prior art [4]. In the FIG. 1, DCMP means decompressor and can be a linear-feedback shift register LFSR. Each core, core 1, core 2, core 3 and core 4, has its own decoder. In addition, a control unit 14 is needed to route seed data 15 to the core designated by the control data. The diagram 20 of FIG. 2 shows how seed streams are packed into one stream, i.e., how tester channels are time-multiplexed. It also shows how control data are determined. Cores in an SoC are compressed individually using LFSR reseeding. Tester channels are time-multiplexed to transfer seed data to the on-Chip decompressors when necessary. To perform seed calculation, test patterns of each core are first split into blocks of fixed length. A seed is obtained by solving linear equations formed by care bits from variable number of blocks. As many as possible blocks are concatenated before a new seed is generated. When an LFSR decoder is expanding a seed to a series of blocks, it does not need to receive data from the tester, until all blocks encoded by this seed have been generated. Hence, seed streams for different cores can be time-multiplexed (or packed) together into a single stream. The overall test application time is therefore reduced by testing cores simultaneously in a time-multiplexing fashion.
The major drawback of architecture of FIG. 1 is that extra data and on-Chip hardware are needed to enable the time-multiplexing mechanism. To keep the multiplexing mechanism easy-to-implement, [4] resorts to fixed length blocks, which will however decrease the encoding efficiency. An optimal block length for one core is not necessarily optimal for other cores.
The diagram 30 of FIG. 3 shows the XNet architecture used in prior art [5]. The LFSR and the phase shifter of the invention shown in FIG. 4A are replaced by a shift register (SR) 31 and an XOR network 32 called XNet. A data word is loaded into the SR to generate a pattern for a scan slice. If a pattern for a scan slice has many care bits, then it may not be possible to find a data word that can justify the pattern for the slice. To account for this problem, a separate load control stream is provided from the automatic test equipment ATE to control operation of the wrapper scan chains WSCs (WSC1, WSC2, WSC3, WSC4), which feed into the multiple input shift register MISR. If values required for some WSCs cannot be justified in a cycle, then the only WSCs for which values are justified are loaded with new values and the other WSCs hold. Then another data word is loaded into the shift register SR 31 to load the rest of the WSCs, which were not loaded in the previous cycle. Since the operation of each WSC should be individually controlled, data to generate load streams can be significant. Hence, achieving high compression by this scheme is difficult.
Accordingly, there is a need for a method applicable to an SoC chip that reduces test application time and achieves maximum compression.